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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 11:09:12 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 11:09:12 -0700 |
| commit | b8dfda876795dbf08bec49ab06ac8603025d2114 (patch) | |
| tree | 35cd5485c70c17e93426d54a104018bae90ed924 /backends/verilog | |
| parent | 6d2ea6fe5563205c0f565810d615c4900d4508d8 (diff) | |
| parent | 22035c20ff071ec5c30990258850ecf97de5d5b3 (diff) | |
| download | yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.tar.gz yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.tar.bz2 yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6818edb7a..83d83f488 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1673,6 +1673,8 @@ struct VerilogBackend : public Backend { bool blackboxes = false; bool selected = false; + auto_name_map.clear(); + reg_wires.clear(); reg_ct.clear(); reg_ct.insert("$dff"); @@ -1779,6 +1781,8 @@ struct VerilogBackend : public Backend { dump_module(*f, "", it->second); } + auto_name_map.clear(); + reg_wires.clear(); reg_ct.clear(); } } VerilogBackend; |