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| author | Jannis Harder <me@jix.one> | 2022-11-25 17:40:50 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | 99163fb822b08503fc99427d5368e24ab325b89b (patch) | |
| tree | 147a9e7d68977ffc723ec75708b5a1f61b5e80e3 /backends/verilog | |
| parent | 605d127517163f3d1113a6dbf19abcd55eb63dbb (diff) | |
| download | yosys-99163fb822b08503fc99427d5368e24ab325b89b.tar.gz yosys-99163fb822b08503fc99427d5368e24ab325b89b.tar.bz2 yosys-99163fb822b08503fc99427d5368e24ab325b89b.zip | |
simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions