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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 10:33:16 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 10:33:16 -0700 |
| commit | 93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586 (patch) | |
| tree | bd0fd95d0728b7b356fd20d9d546eb431701a26a /backends/verilog | |
| parent | b41d2fb4e49a5ee8cda1906405f32614b39302bc (diff) | |
| download | yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.tar.gz yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.tar.bz2 yosys-93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586.zip | |
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Diffstat (limited to 'backends/verilog')
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