diff options
| author | whitequark <whitequark@whitequark.org> | 2020-04-21 15:51:09 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-21 16:14:45 +0000 |
| commit | 4aa0f450f52b595ba1327632a19dc3a989bf2438 (patch) | |
| tree | 77701662eaefd0d3f9d3064a95d39dab2ab89d5e /backends/verilog | |
| parent | 7f5313e6c3c932a82a0fac7719d7c7100342ec77 (diff) | |
| download | yosys-4aa0f450f52b595ba1327632a19dc3a989bf2438.tar.gz yosys-4aa0f450f52b595ba1327632a19dc3a989bf2438.tar.bz2 yosys-4aa0f450f52b595ba1327632a19dc3a989bf2438.zip | |
cxxrtl: use one delta cycle for immediately converging netlists.
If it is statically known that eval() will converge in one delta
cycle (that is, the second commit() will always return `false`)
because the design contains no feedback or buffered wires, then
there is no need to run the second delta cycle at all.
After this commit, the case where eval() always converges immediately
is detected and the second delta cycle is omitted. As a result,
Minerva SRAM SoC runs ~25% faster.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions