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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-27 15:24:48 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-27 20:44:26 +0200 |
| commit | 436d42c00c2bf1b2eaf84ada388d8aaab65da086 (patch) | |
| tree | ddef55a459277faab091276d37726cc94c0e46f0 /backends/verilog | |
| parent | 9600f20be887b707f6d5d3f74dec58b336e2464e (diff) | |
| download | yosys-436d42c00c2bf1b2eaf84ada388d8aaab65da086.tar.gz yosys-436d42c00c2bf1b2eaf84ada388d8aaab65da086.tar.bz2 yosys-436d42c00c2bf1b2eaf84ada388d8aaab65da086.zip | |
opt_expr: Propagate constants to port connections.
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value. This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions