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| author | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-30 19:43:29 -0800 |
|---|---|---|
| committer | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-31 09:20:16 -0800 |
| commit | 89dc40f162a7f06d15ad489066dd0cc64937fbd7 (patch) | |
| tree | 013a344605252dfb82e0929a7e04d624d8826185 /backends/verilog/verilog_backend.cc | |
| parent | 34969d41405a1ad418b82caa394f880ea0f6243f (diff) | |
| download | yosys-89dc40f162a7f06d15ad489066dd0cc64937fbd7.tar.gz yosys-89dc40f162a7f06d15ad489066dd0cc64937fbd7.tar.bz2 yosys-89dc40f162a7f06d15ad489066dd0cc64937fbd7.zip | |
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions