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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:04:20 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:04:20 -0800 |
| commit | 81abb2517c3d6e8fd2b31ff6d9d019d956a6bc14 (patch) | |
| tree | c64df65f19414b166128231218f0f595d93fa58a /backends/verilog/verilog_backend.cc | |
| parent | 970f854c2ad271098b841e61b1d37a61cd04e252 (diff) | |
| parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
| download | yosys-81abb2517c3d6e8fd2b31ff6d9d019d956a6bc14.tar.gz yosys-81abb2517c3d6e8fd2b31ff6d9d019d956a6bc14.tar.bz2 yosys-81abb2517c3d6e8fd2b31ff6d9d019d956a6bc14.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 60668f1f0..d351a6266 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1310,6 +1310,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + std::stringstream ss; + dump_reg_init(ss, cell->getPort("\\Q")); + if (!ss.str().empty()) { + f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); + f << ss.str(); + f << ";\n"; + } + } } void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) |