From 8241db6960d17469678e8c71fd7d6c1b7ddc4fe7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 6 Feb 2019 14:17:09 -0800 Subject: write_verilog to cope with init attr on q when -noexpr --- backends/verilog/verilog_backend.cc | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a7f329ef8..04191443a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1247,7 +1247,30 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_attributes(f, indent, cell->attributes); f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); - if (!defparam && cell->parameters.size() > 0) { + std::string init; + if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + auto q_wire = cell->getPort("\\Q"); + + Const initval; + bool gotinit = false; + + for (auto bit : active_sigmap(q_wire)) { + if (active_initdata.count(bit)) { + initval.bits.push_back(active_initdata.at(bit)); + gotinit = true; + } else { + initval.bits.push_back(State::Sx); + } + } + + if (gotinit) { + std::stringstream ss; + dump_const(ss, initval); + init = ss.str(); + } + } + + if (!defparam && (cell->parameters.size() > 0 || !init.empty())) { f << stringf(" #("); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { if (it != cell->parameters.begin()) @@ -1257,6 +1280,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(")"); } + if (!init.empty()) { + if (!cell->parameters.empty()) + f << stringf(","); + f << stringf("\n%s .INIT(%s)", indent.c_str(), init.c_str()); + } f << stringf("\n%s" ")", indent.c_str()); } @@ -1298,13 +1326,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } f << stringf("\n%s" ");\n", indent.c_str()); - if (defparam && cell->parameters.size() > 0) { + if (defparam && (cell->parameters.size() > 0 || !init.empty())) { for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str()); bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0; dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(";\n"); } + if (!init.empty()) + f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str()); } } -- cgit v1.2.3 From c373640a3ac6c2f76f0a8dce4e44236154ca24bc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 6 Feb 2019 14:28:44 -0800 Subject: Refactor --- backends/verilog/verilog_backend.cc | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 04191443a..66a9e70d3 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o } } -void dump_reg_init(std::ostream &f, SigSpec sig) +void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true) { Const initval; bool gotinit = false; @@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig) } if (gotinit) { - f << " = "; + if (write_equals) f << " = "; dump_const(f, initval); } } @@ -1249,25 +1249,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) std::string init; if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { - auto q_wire = cell->getPort("\\Q"); - - Const initval; - bool gotinit = false; - - for (auto bit : active_sigmap(q_wire)) { - if (active_initdata.count(bit)) { - initval.bits.push_back(active_initdata.at(bit)); - gotinit = true; - } else { - initval.bits.push_back(State::Sx); - } - } - - if (gotinit) { - std::stringstream ss; - dump_const(ss, initval); - init = ss.str(); - } + std::stringstream ss; + dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); + init = ss.str(); } if (!defparam && (cell->parameters.size() > 0 || !init.empty())) { -- cgit v1.2.3 From 20ca795b87b810063cdcee6e92e3922281f6b092 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 6 Feb 2019 14:53:40 -0800 Subject: Remove check for cell->name[0] == '$' --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 66a9e70d3..7b3a60e61 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); std::string init; - if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { std::stringstream ss; dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); init = ss.str(); -- cgit v1.2.3 From 11480b4fa3ba031541e22b52d9ccd658a3e52ff1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 17 Feb 2019 12:18:12 -0800 Subject: Instead of INIT param on cells, use initial statement with hier ref as per @cliffordwolf --- backends/verilog/verilog_backend.cc | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 4b5a13941..d351a6266 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o } } -void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true) +void dump_reg_init(std::ostream &f, SigSpec sig) { Const initval; bool gotinit = false; @@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true) } if (gotinit) { - if (write_equals) f << " = "; + f << " = "; dump_const(f, initval); } } @@ -1250,14 +1250,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_attributes(f, indent, cell->attributes); f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); - std::string init; - if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { - std::stringstream ss; - dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); - init = ss.str(); - } - - if (!defparam && (cell->parameters.size() > 0 || !init.empty())) { + if (!defparam && cell->parameters.size() > 0) { f << stringf(" #("); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { if (it != cell->parameters.begin()) @@ -1267,11 +1260,6 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(")"); } - if (!init.empty()) { - if (!cell->parameters.empty()) - f << stringf(","); - f << stringf("\n%s .INIT(%s)", indent.c_str(), init.c_str()); - } f << stringf("\n%s" ")", indent.c_str()); } @@ -1313,17 +1301,24 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } f << stringf("\n%s" ");\n", indent.c_str()); - if (defparam && (cell->parameters.size() > 0 || !init.empty())) { + if (defparam && cell->parameters.size() > 0) { for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str()); bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0; dump_const(f, it->second, -1, 0, false, is_signed); f << stringf(";\n"); } - if (!init.empty()) - f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str()); } + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + std::stringstream ss; + dump_reg_init(ss, cell->getPort("\\Q")); + if (!ss.str().empty()) { + f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); + f << ss.str(); + f << ";\n"; + } + } } void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) -- cgit v1.2.3