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| author | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-31 08:55:49 -0800 |
|---|---|---|
| committer | Rick Altherr <kc8apf@kc8apf.net> | 2016-01-31 09:20:16 -0800 |
| commit | 0265d7b1006e0946eb4635d73a6d49d31b3e4235 (patch) | |
| tree | 3661ebb9cad772243169a52189cd5a0da9813843 /backends/verilog/verilog_backend.cc | |
| parent | 89dc40f162a7f06d15ad489066dd0cc64937fbd7 (diff) | |
| download | yosys-0265d7b1006e0946eb4635d73a6d49d31b3e4235.tar.gz yosys-0265d7b1006e0946eb4635d73a6d49d31b3e4235.tar.bz2 yosys-0265d7b1006e0946eb4635d73a6d49d31b3e4235.zip | |
rtlil: speed up SigSpec::sort_and_unify()
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup. In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups. Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss. Instead, sort the vector<> that already exists and then apply
std::unique().
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
0 files changed, 0 insertions, 0 deletions