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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:13:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:13:16 -0800 |
| commit | d7ada6649766cfa32b077a744e066476278afd02 (patch) | |
| tree | 02c3b465d2cbcd2a29a58918c6a717bfd1251bfd /backends/aiger/xaiger.cc | |
| parent | 52a27700e2b985d56821ffefb3c61f88cfb96e1a (diff) | |
| download | yosys-d7ada6649766cfa32b077a744e066476278afd02.tar.gz yosys-d7ada6649766cfa32b077a744e066476278afd02.tar.bz2 yosys-d7ada6649766cfa32b077a744e066476278afd02.zip | |
Add "synth_xilinx -dff" option, cleanup abc9
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 80077c10a..d27e0cde5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -251,7 +251,7 @@ struct XAigerWriter RTLIL::Module* inst_module = module->design->module(cell->type); if (inst_module) { - bool abc9_box = inst_module->attributes.count("\\abc9_box_id"); + bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep"); for (const auto &conn : cell->connections()) { auto port_wire = inst_module->wire(conn.first); @@ -403,7 +403,8 @@ struct XAigerWriter log_assert(cell); RTLIL::Module* box_module = module->design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc9_box_id")) + if (!box_module || !box_module->attributes.count("\\abc9_box_id") + || cell->get_bool_attribute("\\abc9_keep")) continue; bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); |