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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
| commit | d7763634b68a735443c61aa32918ee0cdd6e9250 (patch) | |
| tree | d04a1d072d727d0776c42f68668785403cc92bf5 /README | |
| parent | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (diff) | |
| download | yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.gz yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.bz2 yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.zip | |
After reading the SV spec, using non-standard predict() instead of expect()
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -384,8 +384,8 @@ from SystemVerilog: form. In module context: "assert property (<expression>);" and within an always block: "assert(<expression>);". It is transformed to a $assert cell. -- The "assume" and "expect" statements from SystemVerilog are also - supported. The same limitations as with the "assert" statement apply. +- The "assume" statements from SystemVerilog are also supported. The same + limitations as with the "assert" statement apply. - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. |