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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
| commit | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (patch) | |
| tree | 3573f744b6d7c33f55dd06a152d4ff199cf30b22 /README | |
| parent | b3155af5f65333d272da339222e1e1962fb088b7 (diff) | |
| download | yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.gz yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.bz2 yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.zip | |
Added basic support for $expect cells
Diffstat (limited to 'README')
| -rw-r--r-- | README | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -384,9 +384,16 @@ from SystemVerilog: form. In module context: "assert property (<expression>);" and within an always block: "assert(<expression>);". It is transformed to a $assert cell. +- The "assume" and "expect" statements from SystemVerilog are also + supported. The same limitations as with the "assert" statement apply. + - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. +- SystemVerilog packages are supported. Once a SystemVerilog file is read + into a design with "read_verilog", all its packages are available to + SystemVerilog files being read into the same design afterwards. + Building the documentation ========================== |