From 721f1f5ecfb6334904f6058d6d376d21b5efc438 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Jul 2016 16:56:17 +0200 Subject: Added basic support for $expect cells --- README | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'README') diff --git a/README b/README index 50105ed2d..2a1dde435 100644 --- a/README +++ b/README @@ -384,9 +384,16 @@ from SystemVerilog: form. In module context: "assert property ();" and within an always block: "assert();". It is transformed to a $assert cell. +- The "assume" and "expect" statements from SystemVerilog are also + supported. The same limitations as with the "assert" statement apply. + - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. +- SystemVerilog packages are supported. Once a SystemVerilog file is read + into a design with "read_verilog", all its packages are available to + SystemVerilog files being read into the same design afterwards. + Building the documentation ========================== -- cgit v1.2.3