From fb7f02be5561ccfd5bee5f3235fbbae5ef618f36 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 20 Apr 2019 22:24:50 +0200 Subject: New behavior for front-end handling of whiteboxes Signed-off-by: Clifford Wolf --- README.md | 3 +++ 1 file changed, 3 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 5c94c34e5..7f90cb3c2 100644 --- a/README.md +++ b/README.md @@ -316,6 +316,9 @@ Verilog Attributes and non-standard features ``blackbox``, but is for whitebox modules, i.e. library modules that contain a behavioral model of the cell type. +- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog`` + is run in `-lib` mode. Otherwise it's automatically removed. + - The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- cgit v1.2.3