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| author | Asu <sdelang@sdelang.fr> | 2020-04-22 20:50:13 +0200 |
|---|---|---|
| committer | Asu <sdelang@sdelang.fr> | 2020-04-22 20:53:12 +0200 |
| commit | dc77563a6a0b0a812fa006a286e0ec6e091dbd3a (patch) | |
| tree | a09e3a6381cb18d8d8c0e30b94017ead6d987f00 /README.md | |
| parent | db27f2f3786fa867bf7524aff6a5b72c89932620 (diff) | |
| download | yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.tar.gz yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.tar.bz2 yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.zip | |
cxxrtl: keep the memory write queue sorted on insertion.
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.
The Minerva SRAM SoC runs ~7% faster as a result.
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