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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:01:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:01:31 -0700 |
| commit | feb3fa65a3267acda76b7b6eea0e9ffedb281b85 (patch) | |
| tree | f635a53fa7e999dc6bdb9f05559baef445f2f2f4 /CHANGELOG | |
| parent | b08797da6bf0061073dc662441e03b2fd218f11f (diff) | |
| parent | 486cbddd26a8db5bb2f2bbe3ea15e36b6c53a55e (diff) | |
| download | yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.tar.gz yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.tar.bz2 yosys-feb3fa65a3267acda76b7b6eea0e9ffedb281b85.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -38,6 +38,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") + - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones - Added "xilinx_dsp" for Xilinx DSP packing - "synth_xilinx" to now infer DSP blocks (-nodsp to disable) |