From fd7921776387a05edadcc90d1300670d49a73d68 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 27 May 2021 20:54:29 +0200
Subject: Add v2 memory cells.

---
 CHANGELOG | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'CHANGELOG')

diff --git a/CHANGELOG b/CHANGELOG
index 6948ff441..713ae1b50 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -71,6 +71,11 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
     - Added $meminit_v2 cells (with support for write mask)
+    - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
+      - write priority masks, per write/write port pair
+      - transparency and undefined collision behavior masks, per read/write port pair
+      - read port reset and initialization
+      - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------
-- 
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