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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 15:02:46 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 15:02:46 -0800 |
| commit | fce6bad6ae22a3e14115202b05b50ae4a69b5a93 (patch) | |
| tree | 14e5a13254572a48b265f81b8390be34e22e6d05 /CHANGELOG | |
| parent | bea15b537b4b988f24385338c5f25c2b37b66353 (diff) | |
| download | yosys-fce6bad6ae22a3e14115202b05b50ae4a69b5a93.tar.gz yosys-fce6bad6ae22a3e14115202b05b50ae4a69b5a93.tar.bz2 yosys-fce6bad6ae22a3e14115202b05b50ae4a69b5a93.zip | |
Remove 'clkpart' entry in CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -53,7 +53,6 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) - - Added "clkpart" pass Yosys 0.8 .. Yosys 0.9 ---------------------- |