From f7023d06a2bda56467c8f07cc44d3b92f0eab2ba Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 9 Aug 2022 15:43:26 +0200
Subject: sim: -hdlname option to preserve flattened hierarchy in sim output

---
 CHANGELOG | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'CHANGELOG')

diff --git a/CHANGELOG b/CHANGELOG
index 6403c5b9a..a1f4624ee 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -9,6 +9,8 @@ Yosys 0.20 .. Yosys 0.20-dev
     - Added option "-formal" to "memory_map" pass
     - Added option "-witness" to "rename" - give public names to all signals
       present in yosys witness traces
+    - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
+      simulation output for a flattened design
 
  * Formal Verification
     - Added $anyinit cell to directly represent FFs with an unconstrained
-- 
cgit v1.2.3