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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:22:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:22:07 -0700 |
| commit | f6c354c55bcba26978c8dd04c3cc4f02231aebe4 (patch) | |
| tree | 4d1070046f546f6c7cd88d9dd9da48b24f1923bb /CHANGELOG | |
| parent | 7e773741ab4bb7f783e8c2255551fa234ba4672b (diff) | |
| download | yosys-f6c354c55bcba26978c8dd04c3cc4f02231aebe4.tar.gz yosys-f6c354c55bcba26978c8dd04c3cc4f02231aebe4.tar.bz2 yosys-f6c354c55bcba26978c8dd04c3cc4f02231aebe4.zip | |
Update CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -16,7 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass - - Added "shregmap -tech xilinx", used by "synth_xilinx" + - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" Yosys 0.7 .. Yosys 0.8 |