From cffec1f95f0ac4bad1deb24bf7f921bd93145a16 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 24 May 2022 14:32:14 +0200
Subject: verilog: fix signedness when removing unreachable cases

---
 CHANGELOG | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'CHANGELOG')

diff --git a/CHANGELOG b/CHANGELOG
index 4004c534b..ff7ce49a2 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -5,6 +5,11 @@ List of major changes and improvements between releases
 Yosys 0.17 .. Yosys 0.17-dev
 --------------------------
 
+ * Verilog
+    - Fixed an issue where simplifying case statements by removing unreachable
+      cases could result in the wrong signedness being used for comparison with
+      the remaining cases
+
 Yosys 0.16 .. Yosys 0.17
 --------------------------
  * New commands and options
-- 
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