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| author | David Shah <dave@ds0.me> | 2019-11-22 12:46:19 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-11-22 12:46:19 +0000 |
| commit | b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd (patch) | |
| tree | 0688eb03bfee098fe585ae789f6448943a765e15 /CHANGELOG | |
| parent | 49b670ca38988bcce453125166528b32e16f7bb4 (diff) | |
| download | yosys-b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd.tar.gz yosys-b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd.tar.bz2 yosys-b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd.zip | |
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx - Added "check -mapped" + - Added checking of SystemVerilog always block types (always_comb, + always_latch and always_ff) Yosys 0.8 .. Yosys 0.9 ---------------------- |