From b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 22 Nov 2019 12:46:19 +0000
Subject: Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>
---
 CHANGELOG | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'CHANGELOG')

diff --git a/CHANGELOG b/CHANGELOG
index 1fc139d49..a49c27b05 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
     - Added "check -mapped"
+    - Added checking of SystemVerilog always block types (always_comb,
+      always_latch and always_ff)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------
-- 
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