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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:46:56 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:46:56 -0700 |
commit | 9018f29d54cb33328546580e0c7f9ee12e8a4ae3 (patch) | |
tree | d35b854dec4a41747de063803cd622d1da0890a7 /CHANGELOG | |
parent | dda2ec3cc5554f610bfcb86272dfb0a412abad66 (diff) | |
download | yosys-9018f29d54cb33328546580e0c7f9ee12e8a4ae3.tar.gz yosys-9018f29d54cb33328546580e0c7f9ee12e8a4ae3.tar.bz2 yosys-9018f29d54cb33328546580e0c7f9ee12e8a4ae3.zip |
Move CHANGELOG entry from yosys-0.8 to 0.9
Diffstat (limited to 'CHANGELOG')
-rw-r--r-- | CHANGELOG | 8 |
1 files changed, 1 insertions, 7 deletions
@@ -6,18 +6,12 @@ Yosys 0.9 .. Yosys 0.9-dev -------------------------- * Various - - Added "script -select" - - -Yosys 0.9 .. Yosys 0.9-dev --------------------------- - - * Various - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "script -select" Yosys 0.8 .. Yosys 0.8-dev |