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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:46:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:46:32 -0700 |
| commit | dda2ec3cc5554f610bfcb86272dfb0a412abad66 (patch) | |
| tree | c1d7d9f357298c6dd586d6bf323195c8400b3dad /CHANGELOG | |
| parent | fd2fb4f0f0132499ec4db3ce4d85f57c5ab618f8 (diff) | |
| parent | 0067dc44f3928833eede2b9bb40260be78e11a93 (diff) | |
| download | yosys-dda2ec3cc5554f610bfcb86272dfb0a412abad66.tar.gz yosys-dda2ec3cc5554f610bfcb86272dfb0a412abad66.tar.bz2 yosys-dda2ec3cc5554f610bfcb86272dfb0a412abad66.zip | |
Merge branch 'master' into eddie/script_from_wire
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 16 |
1 files changed, 11 insertions, 5 deletions
@@ -9,6 +9,17 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "script -select" +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -32,11 +43,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "synth_xilinx -nocarry" - Added "synth_xilinx -nowidelut" - Added "synth_ecp5 -nowidelut" - - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - - Added "synth_xilinx -abc9" (experimental) - - Added "synth_ice40 -abc9" (experimental) - - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB |