From 7608985d2c6237b869a4774c6b1659282e7473ad Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 15 Dec 2021 18:15:09 -0700 Subject: fix width detection of array querying function in case and case item expressions I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`. --- CHANGELOG | 2 ++ 1 file changed, 2 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 902fe727b..ab1632a09 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,8 @@ Yosys 0.11 .. Yosys 0.12 * SystemVerilog - Support parameters using struct as a wiretype + - Fixed regression preventing the use array querying functions in case + expressions and case item expressions * New commands and options - Added "-genlib" option to "abc" pass -- cgit v1.2.3