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authorClaire Xenia Wolf <claire@clairexen.net>2023-01-11 04:10:12 +0100
committerClaire Xenia Wolf <claire@clairexen.net>2023-01-11 04:10:12 +0100
commit6d56d4ecfc2c9afda3fd58f945a5f10daf87a999 (patch)
tree8b2e2cd5018674f287ae8b2c20877615fec8b555 /CHANGELOG
parent029b0aac7f10ff5e1d927fb6ec1d9571a5350176 (diff)
parent7b476996df962b63656152f643ff2181143f516e (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff
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List of major changes and improvements between releases
=======================================================
-Yosys 0.23 .. Yosys 0.23-dev
+Yosys 0.25 .. Yosys 0.25-dev
--------------------------
+Yosys 0.24 .. Yosys 0.25
+--------------------------
+ * Verific support
+ - Respect "noblackbox" attribute for modules.
+
+ * Various
+ - Documentation is hosted at https://yosyshq.readthedocs.io/projects/yosys/en/latest/
+
+Yosys 0.23 .. Yosys 0.24
+--------------------------
+ * New commands and options
+ - Added option "-set-def-formal" to "sat" pass.
+ - Added option "-s" to "tee" command.
+
* Verilog
- Support for module-scoped identifiers referring to tasks and functions.
+ - Support for arrays with swapped ranges within structs.
+
+ * Verific support
+ - Support for importing verilog configurations per name.
+ - "verific -set-XXXXX" commands are now able to set severity to all messages
+ of certain type (errors, warnings, infos and comments)
+
+ * Various
+ - TCL shell support (use "yosys -C")
+ - Added FABulous eFPGA frontend
Yosys 0.22 .. Yosys 0.23
--------------------------