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authorEddie Hung <eddie@fpgeh.com>2019-06-22 14:40:55 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-22 14:40:55 -0700
commit4ddc0354c1cc61f2e2b3f15cc341fd277c710e89 (patch)
treee93f687e469eb7f2f97bf79d113f03a66c878698 /CHANGELOG
parent545cfbbe0dcc36f18dce6429498f4d87112879e2 (diff)
parentfb8fab4a29e5a3978cadf2b1bd8920b772150028 (diff)
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Merge remote-tracking branch 'origin/master' into eddie/muxpack
Diffstat (limited to 'CHANGELOG')
-rw-r--r--CHANGELOG7
1 files changed, 5 insertions, 2 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 8b93051ea..8c88a7db8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,9 +17,12 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- - Extended "muxcover -mux{4,8,16}=<cost>"
+ - Added "muxcover -mux{4,8,16}=<cost>"
+ - Added "muxcover -dmux=<cost>"
+ - Added "muxcover -nopartial"
- Added "muxpack" pass
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+ - Fixed sign extension of unsized constants with 'bx and 'bz MSB
Yosys 0.7 .. Yosys 0.8
@@ -33,7 +36,7 @@ Yosys 0.7 .. Yosys 0.8
- Added "write_verilog -decimal"
- Added "scc -set_attr"
- Added "verilog_defines" command
- - Remeber defines from one read_verilog to next
+ - Remember defines from one read_verilog to next
- Added support for hierarchical defparam
- Added FIRRTL back-end
- Improved ABC default scripts