From 3b8f3a93ada563fbae62772b0bf642bb54170954 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 12:45:40 -0700 Subject: Add CHANGELOG entry --- CHANGELOG | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 4c38f6e6e..496a521be 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -19,6 +19,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "read_aiger" frontend - Extended "muxcover -mux{4,8,16}=" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - Fixed sign extension of unsized constants with 'bx and 'bz MSB Yosys 0.7 .. Yosys 0.8 @@ -32,7 +33,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts -- cgit v1.2.3 From fb8fab4a29e5a3978cadf2b1bd8920b772150028 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 20:30:24 -0700 Subject: Add 'muxcover -dmux=' and '-nopartial' to CHANGELOG --- CHANGELOG | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 496a521be..128f6c6ff 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend - - Extended "muxcover -mux{4,8,16}=" + - Added "muxcover -mux{4,8,16}=" + - Added "muxcover -dmux=" + - Added "muxcover -nopartial" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - Fixed sign extension of unsized constants with 'bx and 'bz MSB -- cgit v1.2.3