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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-28 16:57:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-28 16:57:03 +0200 |
| commit | fe2ee833e154691ef61cc72833b86e02266039a2 (patch) | |
| tree | 15aea7c5f93273f06fdd70ecdd9dfa57dea2c2d6 | |
| parent | 848c3c5c889945f64ddefc8fe45342a4338dc769 (diff) | |
| download | yosys-fe2ee833e154691ef61cc72833b86e02266039a2.tar.gz yosys-fe2ee833e154691ef61cc72833b86e02266039a2.tar.bz2 yosys-fe2ee833e154691ef61cc72833b86e02266039a2.zip | |
Fix handling of signed memories
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 40cbbc2a3..d9f0039af 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + if (!sign_hint) + is_signed = false; + return RTLIL::SigSpec(wire); } |