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| author | Catherine <whitequark@whitequark.org> | 2021-12-25 01:06:10 +0000 |
|---|---|---|
| committer | Catherine <whitequark@whitequark.org> | 2021-12-25 01:06:10 +0000 |
| commit | fc049e84a91dcfbdbd654be6db222673f6c8f26c (patch) | |
| tree | f41a0b27c52b2f3c9bbd835277792931225ba7c0 | |
| parent | ed4642e18e73e092141b82ef2cad2d7a7f5bd283 (diff) | |
| download | yosys-fc049e84a91dcfbdbd654be6db222673f6c8f26c.tar.gz yosys-fc049e84a91dcfbdbd654be6db222673f6c8f26c.tar.bz2 yosys-fc049e84a91dcfbdbd654be6db222673f6c8f26c.zip | |
cxxrtl: don't reset elided wires with \init attribute.
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index ba11179c6..7a336f8c1 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1838,6 +1838,8 @@ struct CxxrtlWorker { int mem_init_idx = 0; inc_indent(); for (auto wire : module->wires()) { + const auto &wire_type = wire_types[wire]; + if (!wire_type.is_named() || wire_type.is_local()) continue; if (!wire_init.count(wire)) continue; f << indent << mangle(wire) << " = "; |