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| author | Claire Wolf <claire@symbioticeda.com> | 2020-05-17 11:31:11 +0200 |
|---|---|---|
| committer | Claire Wolf <claire@symbioticeda.com> | 2020-05-17 11:31:11 +0200 |
| commit | fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa (patch) | |
| tree | 0f0cfa368da677975a07bca50212ad117e6de88b | |
| parent | 07eecff9cca555086667666c4dbdb4c6a7133c67 (diff) | |
| download | yosys-fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa.tar.gz yosys-fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa.tar.bz2 yosys-fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa.zip | |
Revert "Add support for non-power-of-two mem chunks in verific importer"
This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.
| -rw-r--r-- | frontends/verific/verific.cc | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5f8a78e48..fe4bda68e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize())) + if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1273,11 +1273,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); - if ((numchunks & (numchunks - 1)) != 0) { - addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); - addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); - } - RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); cell->parameters[ID::MEMID] = memory->name.str(); @@ -1300,7 +1295,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size())) + if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1308,11 +1303,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); - if ((numchunks & (numchunks - 1)) != 0) { - addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); - addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); - } - RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); cell->parameters[ID::MEMID] = memory->name.str(); |