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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 20:09:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 20:09:40 -0800 |
| commit | f853b2f3c15f629ea22a9427e5524bdeebddfb8f (patch) | |
| tree | aecaf8c4aada2f1946edf736c6b0b22802a39655 | |
| parent | b9a305b85d17ce61880ee057e19e5ceafd7a6c05 (diff) | |
| download | yosys-f853b2f3c15f629ea22a9427e5524bdeebddfb8f.tar.gz yosys-f853b2f3c15f629ea22a9427e5524bdeebddfb8f.tar.bz2 yosys-f853b2f3c15f629ea22a9427e5524bdeebddfb8f.zip | |
abc9 to write_aiger with -O option, and ignore dummy outputs
| -rw-r--r-- | passes/techmap/abc9.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2cc79fa95..f684ad8de 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -412,8 +412,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design, module); Pass::call(design, "write_verilog -norename -noexpr input.v"); - Pass::call(design, stringf("write_xaiger -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); - Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports -map %s/input.symbols %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str())); // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI @@ -547,6 +547,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { + if (w->name.str() == "\\__dummy_o__") { + log("Don't call ABC as there is nothing to map.\n"); + goto cleanup; + } + auto r = wideports_split(w->name.str()); wire = module->wire(r.first); log_assert(wire); @@ -875,6 +880,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri Pass::call(design, "clean"); +cleanup: if (cleanup) { log("Removing temp directory.\n"); |