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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:22:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:22:14 -0700 |
| commit | f54edf1e78fbcbd8a11c2ffcbdf62a50b93ce909 (patch) | |
| tree | 924761b130fd3fcd80885415f81b3fdfaf66bef9 | |
| parent | efdb057c6ad5ba0fe05a597ba5f080067f061aad (diff) | |
| download | yosys-f54edf1e78fbcbd8a11c2ffcbdf62a50b93ce909.tar.gz yosys-f54edf1e78fbcbd8a11c2ffcbdf62a50b93ce909.tar.bz2 yosys-f54edf1e78fbcbd8a11c2ffcbdf62a50b93ce909.zip | |
Do not call "setundef -zero" in abc9
| -rw-r--r-- | passes/techmap/abc9.cc | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7b13239f2..f652cdf12 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -380,9 +380,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); - // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero - Pass::call(design, "setundef -zero"); - Pass::call(design, "aigmap"); handle_loops(design); @@ -406,7 +403,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri reader.parse_xaiger(); } ifs.close(); - Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v")); + Pass::call(design, stringf("write_verilog -noexpr -norename")); design->remove(design->module("$__abc9__")); #endif @@ -479,7 +476,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri ifs.close(); #if 0 - Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v")); + Pass::call(design, stringf("write_verilog -noexpr -norename")); #endif log_header(design, "Re-integrating ABC9 results.\n"); |