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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2021-10-20 09:07:22 +0200 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-11-10 01:31:39 +0100 |
| commit | f4f5acf396451b88fad99ef947ad733fbea651b6 (patch) | |
| tree | 03585ea2d4bc79dec5f6159b13a2212db9a6112b | |
| parent | 15b0d717ed658b342ce5f74df5a65827eed04a94 (diff) | |
| download | yosys-f4f5acf396451b88fad99ef947ad733fbea651b6.tar.gz yosys-f4f5acf396451b88fad99ef947ad733fbea651b6.tar.bz2 yosys-f4f5acf396451b88fad99ef947ad733fbea651b6.zip | |
genrtlil: Fix displaying debug info in packages
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a68bcd9ee..ed709aa33 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1126,8 +1126,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // everything should have been handled above -> print error if not. default: + AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod; for (auto f : log_files) - current_ast_mod->dumpAst(f, "verilog-ast> "); + current_scope_ast->dumpAst(f, "verilog-ast> "); log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); } |