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authorMiodrag Milanovic <mmicko@gmail.com>2023-03-21 08:53:22 +0100
committermyrtle <gatecat@ds0.me>2023-03-23 09:44:36 +0100
commitf35bdaa5278b408e94ac8c97a06c3f7f0fe1773a (patch)
tree8089e498e0669ce6d0d9338644fe6d5bc4b4424e
parent23826e5152483c39a617ee1c696c3b48a0c2b756 (diff)
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Update Xilinx cell definitions, fixes #3699
-rw-r--r--techlibs/xilinx/cells_sim.v11
-rw-r--r--techlibs/xilinx/cells_xtra.py2
-rw-r--r--techlibs/xilinx/cells_xtra.v9
3 files changed, 16 insertions, 6 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e6e15b16e..8b0c913aa 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -33,8 +33,12 @@ module IBUF(
output O,
(* iopad_external_pin *)
input I);
- parameter IOSTANDARD = "default";
- parameter IBUF_LOW_PWR = 0;
+ parameter CCIO_EN = "TRUE";
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IFD_DELAY_VALUE = "AUTO";
+ parameter IOSTANDARD = "DEFAULT";
assign O = I;
specify
(I => O) = 0;
@@ -56,7 +60,8 @@ module OBUF(
(* iopad_external_pin *)
output O,
input I);
- parameter IOSTANDARD = "default";
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 2630c7a0f..08fe6f35e 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -706,7 +706,7 @@ def xtract_cell_decl(cell, dirs, outf):
if __name__ == '__main__':
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
- parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
+ parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2022.2')
parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
args = parser.parse_args()
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index aae0d3ee5..8dc74b16e 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -7550,10 +7550,12 @@ module IBUF_ANALOG (...);
endmodule
module IBUFE3 (...);
+ parameter CCIO_EN = "TRUE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
- parameter USE_IBUFDISABLE = "FALSE";
+ parameter SIM_DEVICE = "ULTRASCALE";
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ parameter USE_IBUFDISABLE = "FALSE";
output O;
(* iopad_external_pin *)
input I;
@@ -7760,8 +7762,9 @@ module IOBUFE3 (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
- parameter USE_IBUFDISABLE = "FALSE";
+ parameter SIM_DEVICE = "ULTRASCALE";
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ parameter USE_IBUFDISABLE = "FALSE";
output O;
(* iopad_external_pin *)
inout IO;
@@ -19721,6 +19724,7 @@ module HSADC (...);
endmodule
module RFDAC (...);
+ parameter integer LD_DEVICE = 0;
parameter integer OPT_CLK_DIST = 0;
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
parameter integer XPA_ACTIVE_DUTYCYCLE = 100;
@@ -19784,6 +19788,7 @@ module RFDAC (...);
endmodule
module RFADC (...);
+ parameter integer LD_DEVICE = 0;
parameter integer OPT_ANALOG = 0;
parameter integer OPT_CLK_DIST = 0;
parameter SIM_DEVICE = "ULTRASCALE_PLUS";