Merge remote-tracking branch 'origin/read_aiger' into xaig

4 files changed, 12 insertions, 17 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a1b1ecd66..4b5a13941 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1251,7 +1251,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
 	std::string init;
-	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
 		init = ss.str();
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index cc4abe184..56bffcf38 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -316,9 +316,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
     }
 
     log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-    RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
-    inv->setPort("\\A", wire_inv);
-    inv->setPort("\\Y", wire);
+    module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
 
     return wire;
 }
@@ -409,7 +407,7 @@ void AigerReader::parse_aiger_ascii(bool create_and)
         std::getline(f, line); // Ignore up to start of next line
 
     // Parse AND
-    for (unsigned i = 0; i < A; ++i, ++line_count) {
+    for (unsigned i = 0; i < A; ++i) {
         if (!(f >> l1 >> l2 >> l3))
             log_error("Line %u cannot be interpreted as an AND!\n", line_count);
 
@@ -419,14 +417,9 @@ void AigerReader::parse_aiger_ascii(bool create_and)
             RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
             RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
             RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-
-            RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-            and_cell->setPort("\\A", i1_wire);
-            and_cell->setPort("\\B", i2_wire);
-            and_cell->setPort("\\Y", o_wire);
+            module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
         }
     }
-    std::getline(f, line); // Ignore up to start of next line
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d2d15a4a9..b215b1ea4 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -52,6 +52,8 @@
 #include <cerrno>
 #include <sstream>
 #include <climits>
+#include <array>
+#include <functional>
 
 #ifndef _WIN32
 #  include <unistd.h>
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 9b6008140..a1e0c1575 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,7 +1464,7 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
@@ -1484,7 +1484,7 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
@@ -1506,7 +1506,7 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
@@ -1540,7 +1540,7 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
@@ -1563,7 +1563,7 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
@@ -1585,7 +1585,7 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;