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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 23:23:21 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 23:23:21 -0800 |
| commit | eb7dd7d3741983fafe62b13c4a2d6a21ced06133 (patch) | |
| tree | ff78ff272819a0a3656f419660666df49ac0e95c | |
| parent | 2c65e1abacc4401c4fd3e9b48f52c4de120bc511 (diff) | |
| download | yosys-eb7dd7d3741983fafe62b13c4a2d6a21ced06133.tar.gz yosys-eb7dd7d3741983fafe62b13c4a2d6a21ced06133.tar.bz2 yosys-eb7dd7d3741983fafe62b13c4a2d6a21ced06133.zip | |
write_xaiger: fix case of PI and CI and (* keep *)
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 8651f3a01..822ba4dec 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -356,6 +356,11 @@ struct XAigerWriter alias_map[O] = b; ci_bits.emplace_back(b); undriven_bits.erase(O); + // If PI and CI, then must be a (* keep *) wire + if (input_bits.erase(O)) { + log_assert(output_bits.count(O)); + log_assert(O.wire->get_bool_attribute(ID::keep)); + } } } |