diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 10:30:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 10:30:23 +0200 |
| commit | eb1e3caae7e0eeff9d5010748ff77250bab9ae51 (patch) | |
| tree | 0dc999bfd3cc255211b19028ecfaf98ec49f20b3 | |
| parent | ba4cce9f19cf7a8eab78b52ca1aaa4d040eb8e7c (diff) | |
| download | yosys-eb1e3caae7e0eeff9d5010748ff77250bab9ae51.tar.gz yosys-eb1e3caae7e0eeff9d5010748ff77250bab9ae51.tar.bz2 yosys-eb1e3caae7e0eeff9d5010748ff77250bab9ae51.zip | |
Fixed "flatten" for unconnected inout ports
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 30a6d784f..592710eda 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -257,7 +257,7 @@ struct TechmapWorker } else { SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; apply_prefix(cell->name.str(), sig_tpl_pf, module); - for (int i = 0; i < GetSize(sig_tpl); i++) { + for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) { c.first.append(sig_mod[i]); c.second.append(sig_tpl_pf[i]); |