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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:10:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:10:20 -0700 |
| commit | ea6ffea2cd580542cbb5cc349f5268af0700e292 (patch) | |
| tree | a5b846488b3b6653ad629b097c7c035303612b39 | |
| parent | 7899a06ed64c55e8d804ef2970ad983e3d112013 (diff) | |
| download | yosys-ea6ffea2cd580542cbb5cc349f5268af0700e292.tar.gz yosys-ea6ffea2cd580542cbb5cc349f5268af0700e292.tar.bz2 yosys-ea6ffea2cd580542cbb5cc349f5268af0700e292.zip | |
Fix clk_pol for FD*_1
| -rw-r--r-- | backends/aiger/xaiger.cc | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 6 |
2 files changed, 3 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 9a448c2a0..82c28549c 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -311,7 +311,6 @@ struct XAigerWriter alias_map[O] = q; undriven_bits.erase(O); ff_bits.emplace_back(q); - } else { for (const auto &conn : cell->connections()) { diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 6f9011ef1..8e0b578ab 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -157,7 +157,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q, (* abc_flop_d *) input D, input R, \$pastQ ); parameter [0:0] INIT = 1'b0; - parameter \$abc_flop_clk_pol = 1'b1; + parameter \$abc_flop_clk_pol = 1'b0; parameter \$abc_flop_en_pol = 1'b1; assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); endmodule @@ -184,7 +184,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q, (* abc_flop_d *) input D, input CLR, \$pastQ ); parameter [0:0] INIT = 1'b0; - parameter \$abc_flop_clk_pol = 1'b1; + parameter \$abc_flop_clk_pol = 1'b0; parameter \$abc_flop_en_inv = 1'b1; assign Q = (CE && !CLR) ? D : \$pastQ ; endmodule @@ -211,7 +211,7 @@ module \$__ABC_FDPE_1 ((* abc_flop_q *) output Q, (* abc_flop_d *) input D, input PRE, \$pastQ ); parameter [0:0] INIT = 1'b0; - parameter \$abc_flop_clk_pol = ~IS_C_INVERTED; + parameter \$abc_flop_clk_pol = 1'b0; parameter \$abc_flop_en_pol = 1'b1; assign Q = (CE && !PRE) ? D : \$pastQ ; endmodule |