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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 17:45:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 17:45:49 -0700 |
| commit | dc154c39a8d296c0ed7619168d7b4eda95e2fbe0 (patch) | |
| tree | de1ad2f44b9a1aaf0defbd424f7023e814b12d3b | |
| parent | fe722b737ce3dfd359d4f37fb558371c07e6a19c (diff) | |
| download | yosys-dc154c39a8d296c0ed7619168d7b4eda95e2fbe0.tar.gz yosys-dc154c39a8d296c0ed7619168d7b4eda95e2fbe0.tar.bz2 yosys-dc154c39a8d296c0ed7619168d7b4eda95e2fbe0.zip | |
Fix infinite recursion
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cc0857896..4045e8811 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -314,7 +314,7 @@ struct XAigerWriter SigBit d = cell->getPort(abc_flop_d); SigBit I = sigmap(d); if (I != d) - alias_map[I] = d; + alias_map[d] = I; unused_bits.erase(d); auto abc_flop_q = r.first->second.q_port; |