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| author | Lukasz Dalek <ldalek@antmicro.com> | 2020-08-03 17:07:33 +0200 |
|---|---|---|
| committer | Lukasz Dalek <ldalek@antmicro.com> | 2020-08-03 17:07:33 +0200 |
| commit | daee2d967f5785c83123a1afa5b8bdcddf3da1d8 (patch) | |
| tree | 776ec08eda231c141af5697333adf619c92dbd85 | |
| parent | ba08c251333c0002d8cd68d515533ef0614522fd (diff) | |
| download | yosys-daee2d967f5785c83123a1afa5b8bdcddf3da1d8.tar.gz yosys-daee2d967f5785c83123a1afa5b8bdcddf3da1d8.tar.bz2 yosys-daee2d967f5785c83123a1afa5b8bdcddf3da1d8.zip | |
Add test for subarray access on multidimensional arrays
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| -rw-r--r-- | tests/svtypes/multirange_subarray_access.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/svtypes/multirange_subarray_access.ys b/tests/svtypes/multirange_subarray_access.ys new file mode 100644 index 000000000..de57d1423 --- /dev/null +++ b/tests/svtypes/multirange_subarray_access.ys @@ -0,0 +1,12 @@ +logger -expect error "Insufficient number of array indices for a." 1 +read_verilog -sv <<EOT +module foo; +logic a [6:0][4:0][1:0]; +logic b [1:0]; + +assign a[0][0][0] = 1'b0; +assign a[0][0][1] = 1'b1; +assign b = a[0][0]; + +endmodule +EOT |