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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 17:34:22 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 17:34:22 -0700 |
commit | da870e62d9da0e46d3357f11a64af28f0de9043c (patch) | |
tree | 8b108802fc2d168c5eeae3f6fb9d99755be082c8 | |
parent | f66be9433ffab07745c71df25999a7bb17cbb94a (diff) | |
parent | dd4667ef2bfc83a45552e43d9252375df4b8fedf (diff) | |
download | yosys-da870e62d9da0e46d3357f11a64af28f0de9043c.tar.gz yosys-da870e62d9da0e46d3357f11a64af28f0de9043c.tar.bz2 yosys-da870e62d9da0e46d3357f11a64af28f0de9043c.zip |
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
-rw-r--r-- | passes/techmap/muxcover.cc | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index b162fae22..5642aeafc 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -459,25 +459,24 @@ struct MuxcoverWorker mux.cost += prepare_decode_mux(U1, U2, V1, bit); - if (U1 != State::Sx && U2 != State::Sx) { - mux.cost += prepare_decode_mux(T1, T2, U1, bit); - mux.cost += prepare_decode_mux(T3, T4, U2, bit); + mux.cost += prepare_decode_mux(T1, T2, U1, bit); + mux.cost += prepare_decode_mux(T3, T4, U2, bit); + if (U1 != U2 && U1 != State::Sx && U2 != State::Sx) { mux.cost += prepare_decode_mux(T1, T3, V1, bit); - } - if (T1 != T2 && T1 != State::Sx && T2 != State::Sx) { mux.cost += prepare_decode_mux(S1, S2, T1, bit); mux.cost += prepare_decode_mux(S3, S4, T2, bit); - mux.cost += prepare_decode_mux(S1, S3, U1, bit); - } - if (T3 != T4 && T3 != State::Sx && T4 != State::Sx) { + if (T1 != T2 && T1 != State::Sx && T2 != State::Sx) + mux.cost += prepare_decode_mux(S1, S3, U1, bit); + mux.cost += prepare_decode_mux(S5, S6, T3, bit); mux.cost += prepare_decode_mux(S7, S8, T4, bit); - mux.cost += prepare_decode_mux(S5, S7, U2, bit); + if (T3 != T4 && T3 != State::Sx && T4 != State::Sx) + mux.cost += prepare_decode_mux(S5, S7, U2, bit); + + if (T1 != T3 && T1 != State::Sx && T3 != State::Sx) + mux.cost += prepare_decode_mux(S1, S5, V1, bit); } - if (T1 != T2 && T1 != State::Sx && T2 != State::Sx && - T3 != T4 && T3 != State::Sx && T4 != State::Sx) - mux.cost += prepare_decode_mux(S1, S5, V1, bit); mux.selects.push_back(S1); mux.selects.push_back(T1); |