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author | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-23 15:04:31 +0100 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-27 09:24:04 +0100 |
commit | d8cefec1691988a5a842371819be8adb981608de (patch) | |
tree | 7e588d59d96da5363315988bc9b23a47d39936ef | |
parent | 53a4f0fb56f298880c9b91dfa8c2e69a383cd5bc (diff) | |
download | yosys-d8cefec1691988a5a842371819be8adb981608de.tar.gz yosys-d8cefec1691988a5a842371819be8adb981608de.tar.bz2 yosys-d8cefec1691988a5a842371819be8adb981608de.zip |
Added ranged case check
-rw-r--r-- | tests/verific/range_case.sv | 11 | ||||
-rw-r--r-- | tests/verific/range_case.ys | 16 |
2 files changed, 27 insertions, 0 deletions
diff --git a/tests/verific/range_case.sv b/tests/verific/range_case.sv new file mode 100644 index 000000000..9843feafe --- /dev/null +++ b/tests/verific/range_case.sv @@ -0,0 +1,11 @@ +module top(input clk, input signed [3:0] sel_w , output reg out); + +always @ (posedge clk) +begin + case (sel_w) inside + [-4:3] : out <= 1'b1; + [4:5] : out <= 1'b0; + endcase +end + +endmodule diff --git a/tests/verific/range_case.ys b/tests/verific/range_case.ys new file mode 100644 index 000000000..27afbbc17 --- /dev/null +++ b/tests/verific/range_case.ys @@ -0,0 +1,16 @@ +verific -cfg db_abstract_case_statement_synthesis 0 +read -sv range_case.sv +verific -import top +proc +rename top gold + +verific -cfg db_abstract_case_statement_synthesis 1 +read -sv range_case.sv +verific -import top +proc +rename top gate + +miter -equiv -flatten -make_assert gold gate miter +prep -top miter +clk2fflogic +sat -set-init-zero -tempinduct -prove-asserts -verify |