diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-03-19 13:32:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-19 13:32:39 +0100 |
| commit | d8a7fa6b6771245b99af41783cbb3b8c0a12946a (patch) | |
| tree | 7517e095a48b2bcfeee90a163130118689e707f4 | |
| parent | b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d (diff) | |
| download | yosys-d8a7fa6b6771245b99af41783cbb3b8c0a12946a.tar.gz yosys-d8a7fa6b6771245b99af41783cbb3b8c0a12946a.tar.bz2 yosys-d8a7fa6b6771245b99af41783cbb3b8c0a12946a.zip | |
improved $mux optimization in opt_const
| -rw-r--r-- | passes/opt/opt_const.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 1e9b1331b..aa376ae0e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -242,11 +242,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) FOLD_1ARG_CELL(pos) FOLD_1ARG_CELL(neg) + // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == "$mux") { - RTLIL::SigSpec input = cell->connections["\\S"]; - assign_map.apply(input); + RTLIL::SigSpec input = assign_map(cell->connections["\\S"]); + RTLIL::SigSpec inA = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec inB = assign_map(cell->connections["\\B"]); if (input.is_fully_const()) ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]); + else if (inA == inB) + ACTION_DO("\\Y", cell->connections["\\A"]); } next_cell:; |