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authorEddie Hung <eddie@fpgeh.com>2019-06-17 15:10:33 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-17 15:10:33 -0700
commitd80678e581899315791706ee1703bf700b0f9c15 (patch)
tree6f736335f3b11c6ce2ae1680dd4aea01edd1ced5
parent3ebba74461ee7da704212073210eb264c2713c84 (diff)
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Cleanup
-rw-r--r--passes/techmap/abc9.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 776bceb3b..f56350b1d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -527,7 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
- boxes.emplace_back(it->second);
+ boxes.emplace_back(cell);
++it;
}
@@ -629,8 +629,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
- for (auto cell : boxes)
- module->remove(cell);
+ for (auto cell : boxes)
+ module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {