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author | Clifford Wolf <clifford@clifford.at> | 2015-08-16 13:05:32 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-08-16 13:05:32 +0200 |
commit | d5b1a90b33458616c9c002062330c5420335ed31 (patch) | |
tree | c6a2b56cbfd5a7bc30c6ea175f4d8c0991e8fb0e | |
parent | 9c33172ece6969dbca8656789fda8135619ce615 (diff) | |
download | yosys-d5b1a90b33458616c9c002062330c5420335ed31.tar.gz yosys-d5b1a90b33458616c9c002062330c5420335ed31.tar.bz2 yosys-d5b1a90b33458616c9c002062330c5420335ed31.zip |
Added $tribuf and $_TBUF_ sim models
-rw-r--r-- | techlibs/common/simcells.v | 6 | ||||
-rw-r--r-- | techlibs/common/simlib.v | 14 |
2 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 9a820f71c..3b7d55c6e 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -132,6 +132,12 @@ output Y; assign Y = ~((A | B) & (C | D)); endmodule +module \$_TBUF_ (A, E, Y); +input A, E; +output Y; +assign Y = E ? A : 1'bz; +endmodule + module \$_SR_NN_ (S, R, Q); input S, R; output reg Q; diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 275c469b8..2a56b3a1e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1156,6 +1156,20 @@ endmodule `endif // -------------------------------------------------------- +module \$tribuf (A, EN, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +input EN; +output [WIDTH-1:0] Y; + +assign Y = EN ? A : 'bz; + +endmodule + +// -------------------------------------------------------- + module \$assert (A, EN); input A, EN; |