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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-04-03 12:58:29 +0200 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-04-06 09:10:14 +0200 |
| commit | d5a405d3b4c6ab364ec5c9372502a94b84e2fcb1 (patch) | |
| tree | c846672a22d4ee84ac3767b728c63e243bf875af | |
| parent | 6e4c1675e725983da8a11be0eda0b2de47a9f522 (diff) | |
| download | yosys-d5a405d3b4c6ab364ec5c9372502a94b84e2fcb1.tar.gz yosys-d5a405d3b4c6ab364ec5c9372502a94b84e2fcb1.tar.bz2 yosys-d5a405d3b4c6ab364ec5c9372502a94b84e2fcb1.zip | |
Added proper simulation model for CCU2D
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 50 |
1 files changed, 35 insertions, 15 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 1e920329c..2075c0519 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -1,3 +1,9 @@ +module LUT2(input A, B, output Z); + parameter [3:0] INIT = 4'h0; + wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; + assign Z = A ? s1[1] : s1[0]; +endmodule + module LUT4 #( parameter [15:0] INIT = 0 ) ( @@ -300,23 +306,37 @@ module DPR16X4C ( endmodule // --------------------------------------- -(* blackbox *) +(* lib_whitebox *) module CCU2D ( - CIN, - A0, B0, C0, D0, - A1, B1, C1, D1, - S0, S1, COUT + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + output COUT ); - -input CIN; -input A0, B0, C0, D0; -input A1, B1, C1, D1; -output S0, S1, COUT; - -parameter [15:0] INIT0 = 16'h0000; -parameter [15:0] INIT1 = 16'h0000; -parameter INJECT1_0 = "YES"; -parameter INJECT1_1 = "YES"; + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); endmodule (* blackbox *) |