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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:37:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 06:06:32 -0700 |
| commit | d2fed0a7f1bb72ee285657b974f4996c77641a23 (patch) | |
| tree | 4557762241ff614ecaad8eae54e1ab3466d454ef | |
| parent | 2f770b7400f6b12ca13e68496977094f92c13680 (diff) | |
| download | yosys-d2fed0a7f1bb72ee285657b974f4996c77641a23.tar.gz yosys-d2fed0a7f1bb72ee285657b974f4996c77641a23.tar.bz2 yosys-d2fed0a7f1bb72ee285657b974f4996c77641a23.zip | |
nullptr check
| -rw-r--r-- | passes/techmap/abc9.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index cd7954427..52ca47a49 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -124,6 +124,7 @@ void handle_loops(RTLIL::Design *design) RTLIL::SigSpec sig; for (auto b : it->second) { Wire *w = b.wire; + if (!w) continue; if (w->port_output) { log_assert(w->get_bool_attribute("\\abc_scc_break")); w = module->wire(stringf("%s.abci", w->name.c_str())); |