zinit: fix review comments from @mwkmwkmwk

2 files changed, 37 insertions, 9 deletions

diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index fb2f92d4e..b7beb4e9d 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -117,7 +117,7 @@ struct ZinitPass : public Pass {
 						const auto &d = initbits.at(sig_q[i]);
 						initval.bits.push_back(d.first);
 						const auto &b = d.second;
-						b.wire->attributes.at(ID::init)[b.offset];
+						b.wire->attributes.at(ID::init)[b.offset] = State::Sx;
 					} else
 						initval.bits.push_back(all_mode ? State::S0 : State::Sx);
 				}
@@ -126,11 +126,11 @@ struct ZinitPass : public Pass {
 				initwire->attributes[ID::init] = initval;
 
 				for (int i = 0; i < GetSize(initwire); i++)
-					if (initval.bits.at(i) == State::S1)
+					if (initval[i] == State::S1)
 					{
 						sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
 						module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
-						initwire->attributes[ID::init].bits.at(i) = State::S0;
+						initwire->attributes[ID::init][i] = State::S0;
 					}
 					else
 					{
@@ -145,8 +145,9 @@ struct ZinitPass : public Pass {
 
 				if (cell->type == ID($adff)) {
 					auto val = cell->getParam(ID::ARST_VALUE);
-					for (auto &b : val)
-						b = (b == State::S1 ? State::S0 : State::S1);
+					for (int i = 0; i < GetSize(initwire); i++)
+						if (initval[i] == State::S1)
+							val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
 					cell->setParam(ID::ARST_VALUE, std::move(val));
 				}
 				else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index caeab69d3..c74218f7c 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -1,5 +1,5 @@
 read_verilog -icells <<EOT
-module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q);
+module top(input C, R, input [1:0] D, (* init = {2'b10, 2'b01, 1'b1, {8{1'b1}}} *) output [12:0] Q);
 
 (* init = 1'b1 *)
 wire unused;
@@ -13,11 +13,38 @@ $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
 $_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
 $_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
 
-$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8]));
-$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
+$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
+$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
 endmodule
 EOT
-equiv_opt -map +/simcells.v -multiclock zinit
+equiv_opt -assert -map +/simcells.v -multiclock zinit
 design -load postopt
 
+select -assert-count 20 t:$_NOT_
 select -assert-count 1 w:unused a:init %i
+select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input C, R, input [1:0] D, (* init = {2'bx0, 2'b0x, 1'b1, {8{1'b0}}} *) output [12:0] Q);
+
+(* init = 1'b1 *)
+wire unused;
+
+$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
+$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
+$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
+$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
+$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
+$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
+$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
+$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
+
+$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
+$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
+endmodule
+EOT
+select -assert-count 0 t:$_NOT_
+select -assert-count 1 w:unused a:init %i
+select -assert-count 1 w:Q a:init=13'bx00x100000000 %i